Design of an NMOS Parallel Adder

71. R. P. Brent and R. R. Ewin, Design of an NMOS Parallel Adder, AUSMPC Design Community Newsletter 2, Aug. 1982, 1-14. A longer version appeared as Report TR-CS-82-06, Department of Computer Science, Australian National University, May 1982, 41pp; also Appendix E: Testing the Parallel Adder, Sept. 1982, 2pp.

Paper: pdf (1977K).

Abstract

Brent and Kung [60] described a carry lookahead adder which has a regular structure and is suitable for VLSI implementation. This report describes a variant of Brent and Kung's adder and documents the design of a prototype which conforms to the "Mead and Conway" nMOS design rules. The prototype will be fabricated with 5-micron nMOS technology on the first Australian multiproject chip.

Comments

The multiproject chip prototype was successful (see Appendix E). At the time of publication the use of carry-lookahead in VLSI designs was unpopular, but more recently the design technique proposed here has been applied widely in VLSI implementations of adders.

Go to next publication

Return to Richard Brent's index page